Non-volatile memory arrays store information in a memory cell by charging the cell, thereby changing the threshold voltage (Vt) level of the cell, where the threshold voltage is the gate voltage at which current begins to flow across the cell. The state of the stored bit indicates the state of the charge, where a charged cell is programmed and an uncharged cell is unprogrammed. When a sufficiently large voltage is applied to the gate of the memory cell, current will flow if the cell is not programmed but it will not flow if the cell is programmed.
Typically, the state of the cell is sensed by measuring the amount of cell current compared to that of a programmed reference cell when a gate voltage is applied. For a single level memory array, if the cell current is below that of the programmed reference cell (i.e. the cell is programmed), the cell is said to store a first value while if the cell current is above that of the reference cell, the cell is said to store a second value.
FIG. 1, to which reference is now made, illustrates the distribution of cell currents for an array of multi-level cells when a gate voltage GV is applied. In multi-level cells, the amount of charge to be stored varies according to which state is to be represented. For cells with 4 levels, 2 bits may be stored, where each level represents one of the four states. Thus, FIG. 1 shows four curves, each representing one of the four states. The first curve illustrates the distribution 10 of cell currents among the cells of the array, before any of them are programmed. This is called the “native distribution”, with the lowest threshold voltage levels and the highest cell current. The second curve shows the distribution 12 after programming to a first level, the third curve shows the distribution 14 after programming to a second level and the fourth curve shows the distribution 16 after programming to a third level. Note that distributions 12, 14 and 16 have widths Wi, which are very similar, while distribution 10 has width W0, which is typically wider.
The memory chip may have three reference cells, each set at a different level between the distributions. Thus, one reference cell may be programmed to have a reference cell current IREF1 between distribution 10 and distribution 12, the second reference cell may have a reference cell current IREF2 between distribution 12 and distribution 14, and the third reference cell may have a reference cell current IREF3 between distribution 14 and distribution 16. The reference cell currents may be set to maintain margins MxA above a lower distribution and MxB below an upper distribution. For example, margin M2A is set to be above distribution 12 while M2B is below distribution 14. The distance between any two reference cell current levels may be the width of the distribution plus the width of its two margins.
For some types of chips, the cell current level of the first reference cell may be set according to the native distribution while the cell current levels of the remaining reference cells may be set to be a fixed amount below the first reference cell current level.
For reading, a gate voltage GV is provided to the gates of the memory cell to be read and to the gates of the reference cells. The output of the memory cell is compared to the output of each reference cell. If the memory cell is programmed to the highest level, its cell current is the lowest. As a result, the current output of all the reference cells will be larger than the current output of the cell. Similarly, if the memory cell is not programmed, none of the reference cells will provide a higher output current. The other states can also be determined.